307013-003 Datasheet, PDF (81/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel^® ICH7 Pin States
3.3
Output and I/O Signals Planes and States
Table 3-3 and Table 3-4 show the power plane associated with the output and I/O
signals, as well as the state at various times. Within the table, the following terms are
used:
“High-Z”
Tri-state. ICH7 not driving the signal high or low.
“High”
ICH7 is driving the signal to a logic 1
“Low”
ICH7 is driving the signal to a logic 0
“Defined”
Driven to a level that is defined by the function (will be high or
low)
“Undefined”
ICH7 is driving the signal, but the value is indeterminate.
“Running”
Clock is toggling or signal is transitioning because function not
stopping
“Off”
The power plane is off, so ICH7 is not driving
Note that the signal levels are the same in S4 and S5, except as noted.
ICH7 suspend well signal states are indeterminate and undefined and may glitch,
including input signals acting as outputs, prior to RSMRST# deassertion. This does not
apply to LAN_RST#, SLP_S3#, SLP_S4# and SLP_S5#. These signals are determinate
and defined prior to RSMRST# deassertion.
ICH7 core well signal states are indeterminate and undefined and may glitch, including
input signals acting as outputs, prior to PWROK assertion. This does not apply to
FERR# and THRMTRIP#. These signals are determinate and defined prior to PWROK
assertion.
Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only
Configurations (Sheet 1 of 5)
Signal Name
Power
Plane
During
PLTRST#¹ /
RSMRST#²
Immediately
after
PLTRST#¹ /
RSMRST#²
S1
S3_COLD3
PETp[4:1],
PETn[4:1]
PCI Express*
S4/S5
PETp[6:5],
PETn[6:5]
(Intel^® ICH7R and
ICH7DH Only)
Core
DMI[3:0]TXP,
DMI[3:0]TXN
Core
High
High⁴
Defined
Off
Off
DMI
High
High⁴
Defined
Off
Off
Intel ^® ICH7 Family Datasheet
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