307013-003 Datasheet, PDF (724/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.1.42 VC0CTL—VC0 Resource Control Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 114h–117h
Default Value: 800000FFh
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31 VC0 Enable — RO. Hardwired to 1 for VC0.
30:27 Reserved.
26:24 VC0 ID — RO. Hardwired to 0 since the first VC is always assigned as VC0.
23:20 Reserved.
19:17
Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
16
Load Port Arbitration Table — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
15:8 Reserved.
7:0
TC/VC0 Map — R/W, RO. Bit 0 is hardwired to 1 since TC0 is always mapped VC0. Bits
[7:1] are implemented as R/W bits.
19.1.43 VC0STS—VC0 Resource Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 11Ah–11Bh
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:2
1
0
Reserved.
VC0 Negotiation Pending — RO. Hardwired to 0 since this bit does not apply to the
integrated Intel^® High Definition Audio device.
Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
724
Intel ^® ICH7 Family Datasheet