307013-003 Datasheet, PDF (158/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Table 5-28. Causes of SMI# and SCI (Sheet 2 of 2)
Cause^1-5
SCI SMI Additional Enables
TCO SMI — NMI occurred
(and NMIs mapped to SMI)
No
Yes NMI2SMI_EN=1
TCO SMI — INTRUDER#
signal goes active
No
Yes INTRD_SEL=10
TCO SMI — Change of the
BIOSWP bit from 0 to 1
No
Yes BLD=1
TCO SMI — Write attempted
to BIOS
No
Yes BIOSWP=1
BIOS_RLS written to
Yes No
GBL_EN=1
GBL_RLS written to
No
Yes BIOS_EN=1
Write to B2h register
No
Yes APMC_EN = 1
Periodic timer expires
No
Yes PERIODIC_EN=1
64 ms timer expires
No
Yes SWSMI_TMR_EN=1
Enhanced USB Legacy
Support Event
No
Yes LEGACY_USB2_EN = 1
Enhanced USB Intel Specific
Event
No
Yes INTEL_USB2_EN = 1
UHCI USB Legacy logic
No
Yes LEGACY_USB_EN=1
Serial IRQ SMI reported
No
Yes none
Device monitors match
address in its range
No
Yes none
SMBus Host Controller
No
Yes
SMB_SMI_EN
Host Controller Enabled
SMBus Slave SMI message No
Yes none
SMBus SMBALERT# signal
active
No
Yes none
SMBus Host Notify message
received
No
Yes HOST_NOTIFY_INTREN
(Mobile/Ultra Mobile Only)
BATLOW# assertion
Yes
Yes
BATLOW_EN=1.
Access microcontroller 62h/
66h
No
Yes MCSMI_EN
SLP_EN bit written to 1
No
Yes SMI_ON_SLP_EN=1
Where Reported
NMI2SMI_STS
INTRD_DET
BIOSWR_STS
BIOSWR_STS
GBL_STS
BIOS_STS
APM_STS
PERIODIC_STS
SWSMI_TMR_STS
LEGACY_USB2_STS
INTEL_USB2_STS
LEGACY_USB_STS
SERIRQ_SMI_STS
DEVMON_STS,
DEVACT_STS
SMBus host status
reg.
SMBUS_SMI_STS
SMBUS_SMI_STS
SMBUS_SMI_STS
HOST_NOTIFY_STS
BATLOW_STS
MCSMI_STS
SMI_ON_SLP_EN_STS
NOTES:
1.
SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
2.
SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
3.
GBL_SMI_EN must be 1 to enable SMI.
4.
EOS must be written to 1 to re-enable SMI for the next 1.
5.
IICH7 must have SMI# fully enabled when ICH7 is also enabled to trap cycles. If SMI# is
not enabled in conjunction with the trap enabling, then hardware behavior is undefined.
6.
When a power button override first occurs, the system will transition immediately to S5.
The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS)
is not cleared prior to setting SCI_EN.
7.
Only GPI[15:0] may generate an SMI# or SCI.
158
Intel ^® ICH7 Family Datasheet