307013-003 Datasheet, PDF (48/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Introduction
Manageability
In addition to Intel AMT the ICH7 integrates several functions designed to manage the
system and lower the total cost of ownership (TCO) of the system. These system
management functions are designed to report errors, diagnose the system, and recover
from system lockups without the aid of an external microcontroller.
• TCO Timer. The ICH7’s integrated programmable TCO timer is used to detect
system locks. The first expiration of the timer generates an SMI# that the system
can use to recover from a software lock. The second expiration of the timer causes
a system reset to recover from a hardware lock.
• Processor Present Indicator. The ICH7 looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, the ICH7
will reboot the system.
• ECC Error Reporting. When detecting an ECC error, the host controller has the
ability to send one of several messages to the ICH7. The host controller can
instruct the ICH7 to generate either an SMI#, NMI, SERR#, or TCO interrupt.
• Function Disable. The ICH7 provides the ability to disable the following integrated
functions: AC ’97 Modem, AC ’97 Audio, IDE, LAN, USB, LPC, Intel HD Audio, SATA,
or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI
configuration space. Also, no interrupts or power management events are
generated from the disable functions.
• Intruder Detect. The ICH7 provides an input signal (INTRUDER#) that can be
attached to a switch that is activated by the system case being opened. The ICH7
can be programmed to generate an SMI# or TCO interrupt due to an active
INTRUDER# signal.
System Management Bus (SMBus 2.0) (Desktop and Mobile Only)
The ICH7 contains an SMBus Host interface that allows the processor to communicate
with SMBus slaves. This interface is compatible with most I²C devices. Special I²C
commands are implemented.
The ICH7’s SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the ICH7 supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports
eight command protocols of the SMBus interface (see System Management Bus
(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
ICH7’s SMBus also implements hardware-based Packet Error Checking for data
robustness and the Address Resolution Protocol (ARP) to dynamically provide address
to all SMBus devices.
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Intel ^® ICH7 Family Datasheet