307013-003 Datasheet, PDF (769/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)
21.1.3
SPIA—SPI Address Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 04h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
21.1.4
Bit
Description
31:24 Reserved
23:0
SPI Cycle Address (SCA) — R/W. This field is shifted out as the SPI Address (MSb
first). Bits 23:0 correspond to Address bits 23:0.
SPID[N] —SPI Data N Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPI Data [0]: SPIBAR + 08hAttribute:
SPI Data [1]: SPIBAR + 10h
SPI Data [2]: SPIBAR + 18h
SPI Data [3]: SPIBAR + 20h
SPI Data [4]: SPIBAR + 28h
SPI Data [5]: SPIBAR + 30h
SPI Data [6]: SPIBAR + 38h
SPI Data [7]: SPIBAR + 40h
Default Value: See Notes 1 and 2 below
Size:
R/W
64 bits
Bit
Description
SPI Cycle Data [N] (SCD[N]) — R/W. This field is shifted out as the SPI Data on the
Master-Out Slave-In Data pin during the data portion of the SPI cycle. The SCD[N]
register does not begin shifting until SPID[N-1] has completely shifted in/out.
This register also shifts in the data from the Master-In Slave-Out pin into this register
during the data portion of the SPI cycle.
63:0
NOTE: The data is always shifted starting with the least significant byte, msb to lsb,
followed by the next least significant byte, msb to lsb, etc. Specifically, the shift
order on SPI in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-
…8-23-22-…16-31…24-39..32…etc. Bit 56 is the last bit shifted out/in. There are
no alignment assumptions; byte 0 always represents the value specified by the
cycle address.
NOTE: The data in this register may be modified by the hardware during any
programmed SPI transaction. Direct Memory Reads do not modify the contents
of this register.
NOTES:
1.
For SPI Data [7:1] Registers Only: Default value is 0000000000000000h.
2.
For SPI Data 0 Register default value only: This register is initialized to 0 by the reset
assertion. However, the least significant byte of this register is loaded with the first Status
Register read of the Atomic Cycle Sequence that the hardware automatically runs out of
reset. Therefore, bit 0 of this register can be read later to determine if the platform
encountered the boundary case in which the SPI flash was busy with an internal instruction
when the platform reset deasserted.
Intel ^® ICH7 Family Datasheet
769