307013-003 Datasheet, PDF (445/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
Bit
Description
10
(Mobile/
Ultra
Mobile
Only)
BATLOW_EN — R/W. (Mobile/Ultra Mobile Only)
0 = Disable.
1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the SCI_EN
bit) when it goes low. This bit does not prevent the BATLOW# signal from
inhibiting the wake event.
9
(Desktop
and
Mobile
Only)
PCI_EXP_EN — R/W.
0 = Disable SCI generation upon PCI_EXP_STS bit being set.
1 = Enables Intel^® ICH7 to cause an SCI when PCI_EXP_STS bit is set. This is used to
allow the PCI Express* ports, including the link to the (G)MCH, to cause an SCI
due to wake/PME events.
9
(Ultra
Mobile
Only)
Reserved. Must be programmed to 0.
RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not
affected by a hard reset caused by a CF9h write.
8
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
7
Reserved
TCOSCI_EN — R/W.
6
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
AC97_EN — R/W.
0 = Disable.
5
1 = Enables the setting of the AC97_STS to generate a wake event.
NOTE: This bit is also used for Intel^® High Definition Audio when the Intel High
Definition Audio host controller is enabled rather than the AC97 host
controller.
USB2_EN — R/W.
4
0 = Disable.
1 = Enables the setting of the USB2_STS to generate a wake event.
USB1_EN — R/W.
3
0 = Disable.
1 = Enables the setting of the USB1_STS to generate a wake event.
SWGPE_EN— R/W. This bit allows software to control the assertion of SWGPE_STS
bit. This bit This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is
written to a 1, hardware will set SWGPE_STS (acts as a level input)
2
If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1s, an SCI will be generated
If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1, then an
SMI# will be generated
Intel ^® ICH7 Family Datasheet
445