307013-003 Datasheet, PDF (368/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)
Offset Address: 2Ch–2Fh
Default Value: 00000000h
Attribute:
Size:
R/WO
32 bits
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be
written only once after PLTRST# de-assertion.
Bit
Description
31:16
Subsystem ID (SSID) — R/WO This is written by BIOS. No hardware action taken on
this value.
15:0
Subsystem Vendor ID (SSVID) — R/WO This is written by BIOS. No hardware action
taken on this value.
10.1.12 CAPP—Capability List Pointer (LPC I/F—D31:F0)
Offset Address: 34h
Default Value: E0h
Attribute:
Size:
Power Well:
RO
8 bits
Core
Bit
Description
7:0 Capability Pointer (CP) — RO. Indicates the offset of the first item.
10.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)
Offset Address: 40h–43h
Default Value: 00000001h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, RO
32 bit
ACPI, Legacy
Core
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These
registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.
Bit
31:16
15:7
6:1
0
Description
Reserved
Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and
TCO logic. This is placed on a 128-byte boundary.
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.
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Intel ^® ICH7 Family Datasheet