307013-003 Datasheet, PDF (531/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.3.2.1
PxCLB—Port [3:0] Command List Base Address Register
(D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 100h
Attribute:
R/W, RO
Port 1: ABAR + 180h (ICH7R and ICH7DH Only)
Port 2: ABAR + 200h
Port 3: ABAR + 280h (ICH7R and ICH7DH Only)
Undefined
Size:
32 bits
12.3.2.2
Bit
Description
31:10
Command List Base Address (CLB) — R/W. Indicates the 32-bit base for the
command list for this port. This base is used when fetching commands to execute. The
structure pointed to by this address range is 1 KB in length. This address must be 1-KB
aligned as indicated by bits 31:10 being read/write.
Note that these bits are not reset on a HBA reset.
9:0 Reserved — RO
PxCLBU—Port [3:0] Command List Base Address Upper
32-Bits Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 104h
Attribute:
R/W
Port 1: ABAR + 184h (ICH7R and ICH7DH Only)
Port 2: ABAR + 204h
Port 3: ABAR + 284h (ICH7R and ICH7DH Only)
Undefined
Size:
32 bits
12.3.2.3
Bit
Description
31:0
Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for
the command list base address for this port. This base is used when fetching
commands to execute.
Note that these bits are not reset on a HBA reset.
PxFB—Port [3:0] FIS Base Address Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 108h
Attribute:
R/W, RO
Port 1: ABAR + 188h (ICH7R and ICH7DH Only)
Port 2: ABAR + 208h
Port 3: ABAR + 288h (ICH7R and ICH7DH Only)
Undefined
Size:
32 bits
Bit
Description
31:8
7:0
FIS Base Address (FB) — R/W. Indicates the 32-bit base for received FISes. The
structure pointed to by this address range is 256 bytes in length. This address must be
256-byte aligned, as indicated by bits 31:3 being read/write.
Note that these bits are not reset on a HBA reset.
Reserved — RO
Intel ^® ICH7 Family Datasheet
531