307013-003 Datasheet, PDF (761/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

High Precision Event Timer Registers
20.1.2
GEN_CONF—General Configuration Register
Address Offset: 010h
Default Value: 00000000 00000000h
Attribute:
Size:
R/W
64 bits
20.1.3
.
Bit
Description
63:2
1
0
Reserved. These bits return 0 when read.
Legacy Replacement Rout (LEG_RT_CNF) — R/W. If the ENABLE_CNF bit and the
LEG_RT_CNF bit are both set, then the interrupts will be routed as follows:
• Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC
• Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC
• Timer 2-n is routed as per the routing in the timer n config registers.
• If the Legacy Replacement Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC)
will have no impact.
• If the Legacy Replacement Rout bit is not set, the individual routing bits for each of the timers
are used.
• This bit will default to 0. BIOS can set it to 1 to enable the legacy replacement routing, or 0 to
disable the legacy replacement routing.
Overall Enable (ENABLE_CNF) — R/W. This bit must be set to enable any of the
timers to generate interrupts.
0 = Disable. The main counter will halt (will not increment) and no interrupts will be
caused by any of these timers. For level-triggered interrupts, if an interrupt is
pending when the ENABLE_CNF bit is changed from 1-to-0, the interrupt status
indications (in the various Txx_INT_STS bits) will not be cleared. Software must
write to the Txx_INT_STS bits to clear the interrupts.
1 = Enable.
NOTE: This bit will default to 0. BIOS can set it to 1 or 0.
GINTR_STA—General Interrupt Status Register
Address Offset: 020h
Default Value: 00000000 00000000h
Attribute:
Size:
R/W, R/WC
64 bits
Bit
Description
63:3
2
1
0
Reserved. These bits will return 0 when read.
Timer 2 Interrupt Active (T02_INT_STS) — R/W. Same functionality as Timer 0.
Timer 1 Interrupt Active (T01_INT_STS) — R/W. Same functionality as Timer 0.
Timer 0 Interrupt Active (T00_INT_STS) — R/WC. The functionality of this bit
depends on whether the edge or level-triggered mode is used for this timer. (default =
0)
If set to level-triggered mode:
This bit will be set by hardware if the corresponding timer interrupt is active. Once the
bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0
to this bit will have no effect.
If set to edge-triggered mode:
This bit should be ignored by software. Software should always write 0 to this bit.
NOTE: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes
will have no effect.
Intel ^® ICH7 Family Datasheet
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