307013-003 Datasheet, PDF (346/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI-to-PCI Bridge Registers (D30:F0)
9.1.1
9.1.2
9.1.3
VID— Vendor Identification Register (PCI-PCI—D30:F0)
Offset Address: 00h–01h
Default Value: 8086h
Attribute:
Size:
RO
16 bits
Bit
15:0
Description
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h.
DID— Device Identification Register (PCI-PCI—D30:F0)
Offset Address: 02h–03h
Default Value: See bit description
Attribute:
Size:
RO
16 bits
Bit
15:0
Description
Device ID — RO.This is a 16-bit value assigned to the PCI bridge. Refer to the Intel^®
I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device
ID Register.
PCICMD—PCI Command (PCI-PCI—D30:F0)
Offset Address: 04h–05h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:11
10
9
8
7
6
5
4
3
Reserved
Interrupt Disable (ID) — RO. Hardwired to 0. The PCI bridge has no interrupts to
disable
Fast Back to Back Enable (FBE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
SERR# Enable (SERR_EN) — R/W.
0 = Disable.
1 = Enable the Intel^® ICH7 to generate an NMI (or SMI# if NMI routed to SMI#) when
the D30:F0 SSE bit (offset 06h, bit 14) is set.
Wait Cycle Control (WCC) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
Parity Error Response (PER) — R/W.
0 = The ICH7 ignores parity errors on the PCI bridge.
1 = The ICH7 will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are
detected on the PCI bridge.
VGA Palette Snoop (VPS) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0, per the PCI
Express* Base Specification, Revision 1.0a
Special Cycle Enable (SCE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a and the PCI- to-PCI Bridge Specification.
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Intel ^® ICH7 Family Datasheet