307013-003 Datasheet, PDF (205/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Figure 5-10. USB Legacy Keyboard Flow Diagram
KBC Accesses
PCI Config
Read, Write
Comb.
Decoder
60 READ
S
D
Clear SMI_60_R
R
EN_SMI_ON_60R
AND
Same for 60W, 64R, 64W
To Individual
"Caused By"
"Bits"
SMI
OR
EN_PIRQD#
AND
To PIRQD#
USB_IRQ
Clear USB_IRQ
S
D
R
EN_SMI_ON_IRQ
AND
To "Caused By" Bit
Table 5-47. USB Legacy Keyboard State Transitions (Sheet 1 of 2)
Current
State
Action
Data
Value
Next
State
Comment
IDLE
IDLE
IDLE
IDLE
IDLE
GateState1
64h / Write
64h / Write
64h / Read
60h / Write
60h / Read
60h / Write
D1h
Not D1h
N/A
Don't Care
N/A
XXh
Standard D1 command. Cycle passed
GateState1 through to 8042. SMI# doesn't go active.
PSTATE (offset C0, bit 6) goes to 1.
IDLE
Bit 3 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
IDLE
Bit 2 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
IDLE
Bit 1 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
IDLE
Bit 0 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
GateState2
Cycle passed through to 8042, even if trap
enabled in Bit 1 in Config Register. No SMI#
generated. PSTATE remains 1. If data value
is not DFh or DDh then the 8042 may chose
to ignore it.
Intel ^® ICH7 Family Datasheet
205