307013-003 Datasheet, PDF (596/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SMBus Controller Registers (D31:F3)
14.2.12 AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3)
Register Offset: SMBASE + 0Dh
Attribute:
R/W
Default Value: 00h
Size:
8 bits
Lockable:
No
Power Well:
Resume
.
Bit
Description
7:2 Reserved
Enable 32-Byte Buffer (E32B) — R/W.
0 = Disable.
1 _{1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as}
opposed to a single register. This enables the block commands to transfer or receive
up to 32-bytes before the Intel^® ICH7 generates an interrupt.
Automatically Append CRC (AAC) — R/W.
0 = ICH7 will Not automatically append the CRC.
0 _{1 = The ICH7 will automatically append the CRC. This bit must not be changed during}
SMBus transactions or undetermined behavior will result. It should be programmed
only once during the lifetime of the function.
14.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 0Eh
Default Value: See below
Attribute:
Size:
R/W, RO
8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
This register is only applicable in the TCO compatible mode.
Bit
Description
7:3 Reserved
SMLINK_CLK_CTL — R/W.
0 = Intel^® ICH7 will drive the SMLINK0 pin low, independent of what the other SMLINK
2
logic would otherwise indicate for the SMLINK0 pin.
1 = The SMLINK0 pin is not overdriven low. The other SMLINK logic controls the state
of the pin. (Default)
SMLINK1_CUR_STS — RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMLINK1 pin. This allows
1 software to read the current state of the pin.
0 = Low
1 = High
SMLINK0_CUR_STS — RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMLINK0 pin. This allows
0 software to read the current state of the pin.
0 = Low
1 = High
596
Intel ^® ICH7 Family Datasheet