307013-003 Datasheet, PDF (717/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.1.25 PCS—Power Management Control and Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 54h–57h
Default Value: 00000000h
Attribute:
Size:
RO, R/W, R/WC
32 bits
Bit
Description
31:24 Data — RO. Does not apply. Hardwired to 0.
23 Bus Power/Clock Control Enable — RO. Does not apply. Hardwired to 0.
22 B2/B3 Support — RO. Does not apply. Hardwired to 0.
21:16 Reserved.
PME Status (PMES) — R/WC.
0 = Software clears the bit by writing a 1 to it.
1 = This bit is set when the Intel^® High Definition Audio controller would normally
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assert the PME# signal independent of the state of the PME_EN bit (bit 8 in this
register)
This bit is in the resume well and only cleared on a power-on reset. Software must not
make assumptions about the reset state of this bit and must set it appropriately.
14:9 Reserved
PME Enable (PMEE) — R/W.
0 = Disable
1 = when set and if corresponding PMES also set, the Intel High Definition Audio
8
controller sets the AC97_STS bit in the GPE0_STS register (PMBASE +28h). The
AC97_STS bit is shared by AC ’97 and Intel High Definition Audio functions since
they are mutually exclusive.
This bit is in the resume well and only cleared on a power-on reset. Software must not
make assumptions about the reset state of this bit and must set it appropriately.
7:2 Reserved
Power State (PS) — R/W. This field is used both to determine the current power state
of the Intel High Definition Audio controller and to set a new power state.
00 = D0 state
11 = D3_HOT state
Others = reserved
NOTES:
1:0 _1.
If software attempts to write a value of 01b or 10b in to this field, the write
operation must complete normally; however, the data is discarded and no state
change occurs.
2.
When in the D3_HOT states, the Intel High Definition Audio controller’s
configuration space is available, but the I/O and memory space are not.
Additionally, interrupts are blocked.
3.
When software changes this value from D3_HOT state to the D0 state, an internal
warm (soft) reset is generated, and software must re-initialize the function.
Intel ^® ICH7 Family Datasheet
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