307013-003 Datasheet, PDF (277/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
7.1.32
LCTL—Link Control Register
Offset Address: 01A8–01A9h
Default Value: 0000h
Attribute:
Size:
R/W
16-bit
7.1.33
Bit
Description
15:8 Reserved
Extended Synch (ES) — R/W. When set, this bit forces extended transmission of
7
FTS ordered sets when exiting L0s prior to entering L0 and extra sequences (Mobile/
Ultra Mobile Only) at exit from L1 prior to entering L0.
6:2 Reserved
1:0
Desktop
Only
Active State Link PM Control (APMC) — R/W. This field indicates whether DMI
should enter L0s.
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
1:0
Mobile/
Ultra
Mobile
Only
Active State Link PM Control (APMC) — R/W. This field indicates whether DMI
should enter L0s or L1 or both.
00 = Disabled
01 = L0s entry enabled
10 = L1 Entry enabled
11 = L0s and L1 Entry enabled
LSTS—Link Status Register
Offset Address: 01AA–01ABh
Default Value: 0041h
Attribute:
Size:
RO
16-bit
Bit
15:10
9:4
3:0
Description
Reserved
Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b).
Mobile/Ultra Mobile only: The ICH7 may also indicate x2 (000010b), depending on
(G)MCH configuration.
Link Speed (LS) — RO. Link is 2.5 Gb/s.
Intel ^® ICH7 Family Datasheet
277