307013-003 Datasheet, PDF (378/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.1.27 FWH_SEL2—Firmware Hub Select 2 Register
(LPC I/F—D31:F0)
Offset Address: D4h–D5h
Default Value: 4567h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:12
FWH_70_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF70 0000h – FF7F FFFFh
FF30 0000h – FF3F FFFFh
11:8
FWH_60_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF60 0000h – FF6F FFFFh
FF20 0000h – FF2F FFFFh
FWH_50_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
7:4
FF50 0000h – FF5F FFFFh
FF10 0000h – FF1F FFFFh
FWH_40_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
3:0
FF40 0000h – FF4F FFFFh
FF00 0000h – FF0F FFFFh
10.1.28 FWH_DEC_EN1—Firmware Hub Decode Enable Register
(LPC I/F—D31:F0)
Offset Address: D8h–D9h
Default Value: FFCFh
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
FWH_F8_EN — RO. This bit enables decoding two 512-KB Firmware Hub memory
ranges, and one
128-KB memory range.
15 0 = Disable
1 = Enable the following ranges for the Firmware Hub
FFF80000h – FFFFFFFFh
FFB80000h – FFBFFFFFh
FWH_F0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
14 ^{0 = Disable.}
1 = Enable the following ranges for the Firmware Hub:
FFF00000h – FFF7FFFFh
FFB00000h – FFB7FFFFh
FWH_E8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
13 ^{0 = Disable.}
1 = Enable the following ranges for the Firmware Hub:
FFE80000h – FFEFFFFh
FFA80000h – FFAFFFFFh
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Intel ^® ICH7 Family Datasheet