307013-003 Datasheet, PDF (696/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.51 PVS — Port Virtual Channel Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 10Eh–10Fh
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:1
0
Reserved.
VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of
the VC Arbitration table when it is being updated. This field is always 0 in the root port
since there is no VC arbitration table.
18.1.52 V0CAP — Virtual Channel 0 Resource Capability Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 110h–113h
Default Value: 00000001h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24
Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table
since the arbitration is fixed.
23 Reserved.
22:16
Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration; therefore, this
field is not used.
15
Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable
transactions.
14
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not just
advanced packet switching transactions.
13:8
7:0
Reserved.
Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed port
arbitration.
696
Intel ^® ICH7 Family Datasheet