307013-003 Datasheet, PDF (325/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.11
Bit
Description
2 ASF Enabled — RO. This bit is set to 1 when the LAN controller is in ASF mode.
TCO Request — R/WC.
1 0 = Software clears this bit by writing a 1 to it.
1 = This bit is set to 1b when the LAN controller is busy with TCO activity.
PME Status — R/WC. This bit is a reflection of the PME Status bit in the Power
Management Control/Status Register (PMCSR).
0 _{0 = Software clears this bit by writing a 1 to it.This also clears the PME Status bit in the}
PMCSR and deasserts the PME signal.
1 = Set upon a wake-up event, independent of the PME Enable bit.
GENCNTL—General Control Register
(LAN Controller—B1:D8:F0)
Offset Address: 1Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4 Reserved. These bits should be set to 0000b.
LAN Connect Software Reset — R/W.
0 = Cleared by software to begin normal LAN Connect operating mode. Software must
3
not attempt to access the LAN Connect interface for at least 1ms after clearing this
bit.
1 = Software can set this bit to force a reset condition on the LAN Connect interface.
2 Reserved. This bit should be set to 0.
Deep Power-Down on Link Down Enable — R/W.
0 = Disable
1
1 = Enable. The Intel^® ICH7’s internal LAN controller may enter a deep power-down
state (sub-3 mA) in the D2 and D3 power states while the link is down. In this
state, the LAN controller does not keep link integrity. This state is not supported for
point-to-point connection of two end stations.
0 Reserved
Intel ^® ICH7 Family Datasheet
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