307013-003 Datasheet, PDF (767/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)
21.1.1
SPIS—SPI Status Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 00h
Default Value: See bit description
Attribute:
Size:
RO, R/WC, R/WLO
16 bits
Bit
15
14:4
3
Description
SPI Configuration Lock-Down — R/WLO.
0 = No Lock-Down (Default)
1 = SPI Static Configuration information in offsets 50h through 6Fh can not be
overwritten. Once set to 1, this bit can only be cleared by a hardware reset.
Reserved
Blocked Access Status — R/WC.
0 = Not blocked (Default)
1 = Hardware sets this bit to 1 when an access is blocked from running on the SPI
interface due to one of the protection policies or when any of the programmed cycle
registers is written while a programmed access is already in progress. This bit is set
for both programmed accesses and direct memory reads that get blocked.
NOTE: This bit remains asserted until cleared by software writing a 1 or hardware
reset.
Cycle Done Status— R/WC.
0 = Not done (Default)
1 = The Intel^® ICH7 sets this bit to 1 when the SPI Cycle completes (i.e., SCIP bit is 0)
after software sets the SCGO bit.
2 _{NOTE: This bit remains asserted until cleared by software writing a 1 or hardware}
reset.
NOTE: Software must make sure this bit is cleared prior to enabling the SPI SMI#
assertion for a new programmed access.
NOTE: This bit gets set after the Status Register Polling sequence completes after reset
deasserts. It is cleared before and during that sequence.
SPI Access Grant — RO. This bit is used by the software to know when the other SPI
master will not be initiating any long transactions on the SPI bus.
0 = Default
1 _{1 = It is set by hardware in response to software setting the SPI Access Request bit and}
completing the Future Pending handshake with the LAN component.
NOTE: This bit is cleared in response to software clearing the SPI Access Request bit.
SPI Cycle In Progress (SCIP) — RO.
0 = Cycle Not in Progress (Default)
1 = Hardware sets this bit when software sets the SPI Cycle Go bit in the Command
register. This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can determine
0
when read data is valid and/or when it is safe to begin programming the next
command.
This bit reports 1b during the Status Register Polling sequence after reset deasserts; it
is cleared when that sequence completes.
NOTE: Software must only program the next command when this bit is 0.
Intel ^® ICH7 Family Datasheet
767