307013-003 Datasheet, PDF (422/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.1.3
GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0)
Offset Address: A4h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, R/WC
8-bit
ACPI, Legacy
RTC
Bit
Description
SWSMI_RATE_SEL — R/W. This field indicates when the SWSMI timer will time out.
Valid values are:
00 = 1.5 ms ± 0.6 ms
7:6 _{01 = 16 ms ± 4 ms}
10 = 32 ms ± 4 ms
11 = 64 ms ± 4 ms
These bits are not cleared by any type of reset except RTCRST#.
SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum
assertion width of the SLP_S4# signal to ensure that the DRAMs have been safely
power-cycled.
Valid values are:
11 = 1 to 2 seconds
10 = 2 to 3 seconds
5:4
01 = 3 to 4 seconds
00 = 4 to 5 seconds
This value is used in two ways:
1.
If the SLP_S4# assertion width is ever shorter than this time, a status bit is set
for BIOS to read when S0 is entered.
2.
If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal
from deasserting within this minimum time period after asserting.
RTCRST# forces this field to the conservative default state (00b)
SLP_S4# Assertion Stretch Enable — R/W.
0 = The SLP_S4# minimum assertion time is 1 to 2 RTCCLK.
3 1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this
register.
This bit is cleared by RTCRST#
422
Intel ^® ICH7 Family Datasheet