307013-003 Datasheet, PDF (456/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.9
System Management TCO Registers (D31:F0)
The TCO logic is accessed via registers mapped to the PCI configuration space
(Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers,
see LPC Device 31:Function 0 PCI Configuration registers.
TCO Register I/O Map
The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which
is, PMBASE + 60h in the PCI configuration space. The following table shows the
mapping of the registers within that 32-byte range. Each register is described in the
following sections.
Table 10-12. TCO I/O Register Address Map
TCOBASE
+ Offset
Mnemonic
Register Name
00h–01h
02h
03h
04h–05h
06h–07h
TCO_RLD
TCO_DAT_IN
TCO_DAT_OUT
TCO1_STS
TCO2_STS
TCO Timer Reload and Current
Value
TCO Data In
TCO Data Out
TCO1 Status
TCO2 Status
08h–09h
TCO1_CNT
TCO1 Control
0Ah–0Bh
0Ch–0Dh
0Eh
0Fh
10h
11h
12h–13h
14h–1Fh
TCO2_CNT
TCO2 Control
TCO_MESSAGE1,
TCO_MESSAGE2
TCO Message 1 and 2
TCO_WDCNT Watchdog Control
—
Reserved
SW_IRQ_GEN Software IRQ Generation
—
Reserved
TCO_TMR
TCO Timer Initial Value
—
Reserved
Default
0000h
00h
00h
0000h
0000h
0000h
0008h
00h
00h
—
11h
—
0004h
—
Type
R/W
R/W
R/W
R/WC, RO
R/W, R/WC
R/W,
R/W
(special),
R/WC
R/W
R/W
R/W
—
R/W
—
R/W
—
10.9.1
TCO_RLD—TCO Timer Reload and Current Value Register
I/O Address:
Default Value:
Lockable:
TCOBASE +00h
0000h
No
Attribute:
Size:
Power Well:
R/W
16-bit
Core
Bit
Description
15:10 Reserved
9:0
TCO Timer Value — R/W. Reading this register will return the current count of the TCO
timer. Writing any value to this register will reload the timer to prevent the timeout.
456
Intel ^® ICH7 Family Datasheet