307013-003 Datasheet, PDF (772/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)
21.1.8
Note:
21.1.9
OPMENU—Opcode Menu Configuration Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 58h
Default Value: 0000000000000005h
Attribute:
Size:
R/W
64 bits
Eight entries are available in this register to give BIOS a sufficient set of commands for
communicating with the flash device, while also restricting what malicious software can
do. This keeps the hardware flexible enough to operate with a wide variety of SPI
devices.
It is recommended that BIOS avoid programming Write Enable opcodes in this menu.
Malicious software could then perform writes and erases to the SPI flash without using
the atomic cycle mechanism. This could cause functional failures in a shared flash
environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.
Bit
Description
63:56
55:48
47:40
39:32
31:24
23:16
15:8
7:0
Allowable Opcode 7 — R/W. See the description for bits 7:0
Allowable Opcode 6 — R/W. See the description for bits 7:0
Allowable Opcode 5 — R/W. See the description for bits 7:0
Allowable Opcode 4 — R/W. See the description for bits 7:0
Allowable Opcode 3 — R/W. See the description for bits 7:0
Allowable Opcode 2 — R/W. See the description for bits 7:0
Allowable Opcode 1 — R/W. See the description for bits 7:0
Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use
when initiating SPI commands through the Control Register.
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15)
is set.
PBR[N]—Protected BIOS Range [N]
(SPI Memory Mapped Configuration Registers)
Memory Address:PBR[0]: SPIBAR + 60h
PBR[1]: SPIBAR + 64h
PBR[2]: SPIBAR + 68h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31
30:24
23:12
Write Protection Enable — R/W.
0 = Disable. The base and limit fields are ignored when this bit is cleared.
1 = Enable. The Base and Limit fields in this register are valid.
Reserved
Protected Range Limit — R/W. This field corresponds to SPI address bits 23:12 and
specifies the upper limit of the protected range.
NOTE: Any address greater than the value programmed in this field is unaffected by
this protected range.
Protected Range Base — R/W. This field corresponds to SPI address bits 23:12 and
specifies the lower base of the protected range.
11:0
NOTE: Address bits 11:0 are assumed to be 000h for the base comparison. Any
address less than the value programmed in this field is unaffected by this
protected range.
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15)
is set.
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Intel ^® ICH7 Family Datasheet