307013-003 Datasheet, PDF (534/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Bit
Description
28
27
26
25
24
23
22
21:8
7
6
5
4
3
2
1
0
Host Bus Data Error Enable (HBDE) — R/W. When set, and GHC.IE and PxS.HBDS
are set, the ICH7 will generate an interrupt.
Host Bus Data Error Enable (HBDE) — R/W. When set, GHC.IE is set, and
PxIS.HBDS is set, the ICH7 will generate an interrupt.
Interface Non-fatal Error Enable (INFE) — R/W. When set, GHC.IE is set, and
PxIS.INFS is set, the ICH7 will generate an interrupt.
Reserved - Should be written as 0
Overflow Error Enable (OFE) — R/W. When set, and GHC.IE and PxS.OFS are set,
the ICH7 will generate an interrupt.
Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and
PxIS.IPMS are set, the ICH7 will generate an interrupt.
NOTE: Should be written as 0. Port Multiplier not supported by ICH7.
PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and
PxIS.PRCS is set, the ICH7 shall generate an interrupt.
Reserved - Should be written as 0
Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the ICH7 will
generate an interrupt.
For systems that do not support an interlock switch, this bit shall be a read-only 0.
Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS
are set, the ICH7 will generate an interrupt.
Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and
PxS.DPS are set, the ICH7 will generate an interrupt
Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an
unknown FIS is received, the ICH7 will generate this interrupt.
Set Device Bits FIS Interrupt Enable (SDBE) — R/W. When set, and GHC.IE and
PxS.SDBS are set, the ICH7 will generate an interrupt.
DMA Setup FIS Interrupt Enable (DSE) — R/W. When set, and GHC.IE and PxS.DSS
are set, the ICH7 will generate an interrupt.
PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PSS
are set, the ICH7 will generate an interrupt.
Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set, and
GHC.IE and PxS.DHRS are set, the ICH7 will generate an interrupt.
534
Intel ^® ICH7 Family Datasheet