307013-003 Datasheet, PDF (814/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Electrical Characteristics
Table 23-23. Power Management Timings (Sheet 1 of 3)
Sym
Parameter
t230
t231
t232
VccSus active to SLP_S5#, SLP_S4#,
SLP_S3#, SUS_STAT#, PLTRST# and
PCIRST#active
RSMRST# inactive to SUSCLK running,
SLP_S5# inactive
t233 SLP_S5# inactive to SLP_S4# inactive
t234 SLP_S4# inactive to SLP_S3# inactive
t250
t253
t254
t255
t265
Processor I/F signals latched prior to
STPCLK# active
(Mobile/Ultra Mobile Only)
DPSLP#/Ultra Mobile active to STP_CPU#
active
(Mobile Only)
STP_CPU# active to processor clock stopped
(Mobile/Ultra Mobile Only)
STP_CPU# active to DPRSTP#, DPRSLPVR
active
(Mobile/Ultra Mobile Only)
Break Event to DPRSTP#, DPRSLPVR
inactive
(C4 Exit)
(Mobile/Ultra Mobile Only)
DPRSLPVR, DPRSTP# inactive to STP_CPU#
t266 inactive and CPU Vcc ramped
(Mobile/Ultra Mobile Only)
t267
t268
t269
t271
t273
t274
Break Event to STP_CPU# inactive
(C3 Exit)
(Mobile/Ultra Mobile Only)
STP_CPU# inactive to processor clock
running
(Mobile/Ultra Mobile Only)
STP_CPU# inactive to DPSLP# inactive
(Mobile/Ultra Mobile Only)
S1 Wake Event to CPUSLP# inactive
(Desktop Only)
Break Event to STPCLK# inactive
(C2 Exit)
(Mobile/Ultra Mobile Only)
STPCLK# inactive to processor I/F signals
unlatched
(Mobile/Ultra Mobile Only)
t280 STPCLK# active to DMI Message
Min Max Units
50
ns
110
ms
See Note Below
1
2 RTCCLK
0
1
1 PCICLK
0
– PCICLK
0
1.5 1.8
µs
Programable.
See
D31:F0:AA,
µs
bits 3:2
6
Note
14
PCICLK
0
3 PCICLK
1
1 PCICLK
1
25 PCICLK
0
ns
8
9 PCICLK
0
PCICLK
Notes
1, 2
3
4
5
6
6, 7
8
6, 9, 10
6, 7
6, 11
6
5, 6
12
Fig
23-20
23-21
23-20
23-21
23-20
23-21
23-20
23-21
23-27
23-29
23-30
23-28
23-29
23-29
23-30
23-29
23-29
23-29
23-28
23-29
23-30
23-28
23-29
23-22
23-27
23-27
23-29
23-30
23-22
23-23
23-24
23-25
23-26
814
Intel ^® ICH7 Family Datasheet