307013-003 Datasheet, PDF (663/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)
Bit
Description
Read Completion Status (RCS) — R/WC. This bit indicates the status of codec read
completions. Software clears this bit by writing a 1 to it.
15 ^{0 = A codec read completes normally.}
1 = A codec read results in a time-out.
NOTE: This bit is not affected by D3_HOT to D0 Reset.
14 Bit 3 of Slot 12 — RO. Display bit 3 of the most recent slot 12.
13 Bit 2 of Slot 12 — RO. Display bit 2 of the most recent slot 12.
12 Bit 1 of Slot 12 — RO. Display bit 1 of the most recent slot 12.
ACZ_SDIN1 Resume Interrupt (S1RI) — R/WC. This bit indicates that a resume
event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it.
11 ^{0 = Resume event did Not occur.}
1 = Resume event occurred.
NOTE: This bit is not affected by D3_HOT to D0 Reset.
ACZ_SDIN0 Resume Interrupt (S0RI) — R/WC. This bit indicates that a resume
event occurred on ACZ_SDIN0. Software clears this bit by writing a 1 to it.
10 ^{0 = Resume event did Not occur.}
1 = Resume event occurred.
NOTE: This bit is not affected by D3_HOT to D0 Reset.
ACZ_SDIN1 Codec Ready (S1CR) — RO. This bit reflects the state of the codec
ready bit in ACZ_SDIN1. Bus masters ignore the condition of the codec ready bits, so
software must check this bit before starting the bus masters. Once the codec is “ready”,
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it must not go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
ACZ_SDIN0 Codec Ready (S0CR) — RO. This bit reflects the state of the codec
ready bit in ACZ_SDIN 0. Bus masters ignore the condition of the codec ready bits, so
software must check this bit before starting the bus masters. Once the codec is “ready”,
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it must not go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
Microphone In Interrupt (MINT) — RO.
7 _{0 = When the specific status bit is cleared, this bit will be cleared.}
1 = One of the Mic in channel interrupts status bits has been set.
PCM Out Interrupt (POINT) — RO.
6 0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the PCM out channel interrupts status bits has been set.
PCM In Interrupt (PIINT) — RO.
5 _{0 = When the specific status bit is cleared, this bit will be cleared.}
1 = One of the PCM in channel interrupts status bits has been set.
4:3 Reserved
Intel ^® ICH7 Family Datasheet
663