307013-003 Datasheet, PDF (67/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Signal Description
Table 2-13. Processor Interface Signals (Sheet 2 of 3)
Name
Type
Description
IGNNE#
INIT#
INIT3_3V#
(Desktop
and Mobile
Only)
INTR
NMI
SMI#
STPCLK#
RCIN#
Ignore Numeric Error: This signal is connected to the ignore error pin
on the processor. IGNNE# is only used if the ICH7 coprocessor error
reporting function is enabled in the OIC.CEN register (Chipset Config
O
Registers:Offset 31FFh: bit 1). If FERR# is active, indicating a coprocessor
error, a write to the Coprocessor Error register (I/O register F0h) causes
the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is
negated. If FERR# is not asserted when the Coprocessor Error register is
written, the IGNNE# signal is not asserted.
Initialization: INIT# is asserted by the ICH7 for 16 PCI clocks to reset
O the processor. ICH7 can be configured to support processor Built In Self
Test (BIST).
O
Initialization 3.3 V: This is the identical 3.3 V copy of INIT# intended
for Firmware Hub.
CPU Interrupt: INTR is asserted by the ICH7 to signal the processor that
O an interrupt request is pending and needs to be serviced. It is an
asynchronous output and normally driven low.
Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt
to the processor. The ICH7 can generate an NMI when either SERR# is
O
asserted or IOCHK# goes active via the SERIRQ# stream. The processor
detects an NMI when it detects a rising edge on NMI. NMI is reset by
setting the corresponding NMI source enable/disable bit in the NMI Status
and Control register (I/O Register 61h).
System Management Interrupt: SMI# is an active low output
O synchronous to PCICLK. It is asserted by the ICH7 in response to one of
many enabled hardware or software events.
Stop Clock Request: STPCLK# is an active low output synchronous to
O
PCICLK. It is asserted by the ICH7 in response to one of many hardware
or software events. When the processor samples STPCLK# asserted, it
responds by stopping its internal clock.
Keyboard Controller Reset CPU: The keyboard controller can generate
INIT# to the processor. This saves the external OR gate with the ICH7’s
other sources of INIT#. When the ICH7 detects the assertion of this
I signal, INIT# is generated for 16 PCI clocks.
NOTE: The ICH7 will ignore RCIN# assertion during transitions to the S1,
S3, S4, and S5 states.
Intel ^® ICH7 Family Datasheet
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