307013-003 Datasheet, PDF (375/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.1.22 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address: 84h – 87h
Default Value: 00000000h
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Bit
Description
31:24 Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16 Reserved
15:2
Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is
aligned on a 128-byte boundary, and must have address lines 31:16 as 0.
NOTE: The Intel^® ICH7 does not provide decode down to the word or byte level.
1 Reserved
Generic Decode Range 1 Enable (GEN1_EN) — R/W.
0 _{0 = Disable.}
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F
10.1.23 GEN2_DEC—LPC I/F Generic Decode Range 2Register
(LPC I/F—D31:F0)
Offset Address: 88h – 8Bh
Default Value: 00000000h
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Bit
Description
31:24 Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16 Reserved
15:2
Generic I/O Decode Range 2Base Address (GEN1_BASE) — R/W.
NOTE: The Intel^® ICH7 does not provide decode down to the word or byte level.
1 Reserved
Generic Decode Range 2Enable (GEN2_EN) — R/W.
0 0 = Disable.
1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F
Intel ^® ICH7 Family Datasheet
375