307013-003 Datasheet, PDF (545/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

EHCI Controller Registers (D29:F7)
13 EHCI Controller Registers
(D29:F7)
13.1
USB EHCI Configuration Registers
(USB EHCI—D29:F7)
Note:
Note:
Register address locations that are not shown in Table 13-1 should be treated as
Reserved (see Section 6.2 for details).
All configuration registers in this section are in the core well and reset by a core well
reset and the D3-to-D0 warm reset, except as noted.
Table 13-1. USB EHCI PCI Register Address Map (USB EHCI—D29:F7) (Sheet 1 of 2)
Offset
Mnemonic
Register Name
Default Val
ue
Type
00h–01h VID
02h–03h DID
04h–05h PCICMD
06h–07h PCISTS
08h
RID
09h
0Ah
0Bh
0Dh
10h–13h
PI
SCC
BCC
PMLT
MEM_BASE
2Ch–2Dh SVID
2Eh–2Fh SID
34h
CAP_PTR
3Ch
INT_LN
3Dh INT_PN
50h
PWR_CAPID
51h
NXT_PTR1
52h–53h PWR_CAP
54h–55h PWR_CNTL_STS
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Primary Master Latency Timer
Memory Base Address
USB EHCI Subsystem Vendor
Identification
USB EHCI Subsystem
Identification
Capabilities Pointer
Interrupt Line
Interrupt Pin
PCI Power Management Capability
ID
8086h
See register
description.
0000h
0290h
See register
description
20h
03h
0Ch
00h
00000000h
XXXXh
XXXXh
50h
00h
See register
description
01h
Next Item Pointer #1
58h
Power Management Capabilities
C9C2h
Power Management Control/Status
0000h
RO
RO
R/W, RO
R/W, RO
RO
RO
RO
RO
RO
R/W, RO
R/W
(special)
R/W
(special)
RO
R/W
RO
RO
R/W
(special)
R/W
(special)
R/W, R/WC,
RO
Intel ^® ICH7 Family Datasheet
545