307013-003 Datasheet, PDF (649/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)
17.1.4
Note:
PCISTS—PCI Status Register (Modem—D30:F3)
Address Offset: 06h–07h
Default Value: 0290h
Lockable:
No
Attribute:
Size:
Power Well:
R/WC, RO
16 bits
Core
PCISTS is a 16-bit status register. Refer to the PCI Local Bus Specification for complete
details on each bit.
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Description
Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0.
Signaled System Error (SSE) —RO. Not implemented. Hardwired to 0.
Master Abort Status (MAS) — R/WC.
0 = Master abort Not generated by bus master AC ‘97 function.
1 = Bus Master AC ‘97 interface function, as a master, generates a master abort.
Reserved. Read as 0.
Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field reflects the ICH7's DEVSEL#
timing parameter. These read only bits indicate the ICH7's DEVSEL# timing when
performing a positive decode.
Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. This bit indicates that the
ICH7 as a target is capable of fast back-to-back transactions.
User Definable Features (UDF) — RO. Not implemented. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Indicates that the controller contains a capabilities
pointer list. The first item is pointed to by looking at configuration offset 34h.
Interrupt Status (INTS) — RO.
0 = This bit is 0 after the interrupt is cleared.
1 = This bit is 1 when the INTx# is asserted.
Reserved
Intel ^® ICH7 Family Datasheet
649