307013-003 Datasheet, PDF (298/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
7.1.55
BUC—Backed Up Control Register
Offset Address: 3414–3414h
Attribute:
Default Value: 0000000xb (Desktop Only)
Size:
0000001xb (Mobile/Ultra Mobile Only)
R/W
8-bit
All bits in this register are in the RTC well and only cleared by RTCRST#.
Bit
Description
7:3 Reserved
CPU BIST Enable (CBE) — R/W. This bit is in the resume well and is reset by
RSMRST#, but not PLTRST# nor CF9h writes.
2
0 = Disabled.
1 = The INIT# signals will be driven active when CPURST# is active. INIT# and
INIT3_3V# will go inactive with the same timings as the other processor I/F
signals (hold time after CPURST# inactive).
1
(Mobile/
Ultra
Mobile
Only)
PATA Reset State (PRS) — R/W.
0 = Disabled.
1 = The reset state of the PATA pins will be driven/tri-state.
1
(Desktop ^Reserved
Only)
Top Swap (TS) — R/W.
0 = Intel^® ICH7 will not invert A16.
1 = ICH7 will invert A16 for cycles going to the BIOS space (but not the feature
0
space) in the FWH.
If the ICH7 is strapped for Top-Swap (GNT3# is low at rising edge of PWROK), then
this bit cannot be cleared by software. The strap jumper should be removed and the
system rebooted.
298
Intel ^® ICH7 Family Datasheet