307013-003 Datasheet, PDF (316/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.1
SCB_STA—System Control Block Status Word Register
(LAN Controller—B1:D8:F0)
Offset Address: 00h–01h
Default Value: 0000h
Attribute:
Size:
R/WC, RO
16 bits
The ICH7’s integrated LAN controller places the status of its Command Unit (CU) and
Receive Unit (RC) and interrupt indications in this register for the processor to read.
Bit
Description
Command Unit (CU) Executed (CX) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
15
position.
1 = Interrupt signaled because the CU has completed executing a command with its
interrupt bit set.
Frame Received (FR) — R/WC.
14 ^{0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit}
position.
1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame.
CU Not Active (CNA) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
13 ^{1 = The Command Unit left the Active state or entered the Idle state. There are 2}
distinct states of the CU. When configured to generate CNA interrupt, the interrupt
will be activated when the CU leaves the Active state and enters either the Idle or
the Suspended state. When configured to generate CI interrupt, an interrupt will be
generated only when the CU enters the Idle state.
Receive Not Ready (RNR) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
12
position.
1 = Interrupt signaled because the Receive Unit left the Ready state. This may be
caused by an RU Abort command, a no resources situation, or set suspend bit due
to a filled Receive Frame Descriptor.
Management Data Interrupt (MDI) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
11
position.
1 = Set when a Management Data Interface read or write cycle has completed. The
management data interrupt is enabled through the interrupt enable bit (bit 29 in
the Management Data Interface Control register in the CSR).
Software Interrupt (SWI) — R/WC.
10 ^{0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit}
position.
1 = Set when software generates an interrupt.
Early Receive (ER) — R/WC.
9 ^{0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit}
position.
1 = Indicates the occurrence of an Early Receive Interrupt.
Flow Control Pause (FCP) — R/WC.
8 ^{0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit}
position.
1 = Indicates Flow Control Pause interrupt.
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Intel ^® ICH7 Family Datasheet