307013-003 Datasheet, PDF (479/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

UHCI Controllers Registers
11.2 USB I/O Registers
Some of the read/write register bits that deal with changing the state of the USB hub
ports function such that on read back they reflect the current state of the port, and not
necessarily the state of the last write to the register. This allows the software to poll the
state of the port and wait until it is in the proper state before proceeding. A host
controller reset, global reset, or port reset will immediately terminate a transfer on the
affected ports and disable the port. This affects the USBCMD register, bit 4 and the
PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail.
Table 11-2. USB I/O Registers
BASE +
Offset
00–01h
02–03h
04–05h
06–07h
08–0Bh
0Ch
0D–0Fh
Mnemonic
Register Name
USBCMD
USBSTS
USBINTR
FRNUM
FRBASEADD
SOFMOD
—
USB Command
USB Status
USB Interrupt Enable
Frame Number
Frame List Base Address
Start of Frame Modify
Reserved
10–11h PORTSC0 Port 0 Status/Control
12–13h PORTSC1 Port 1 Status/Control
Default
Type
0000h
0020h
0000h
0000h
Undefined
40h
—
0080h
0080h
R/W
R/WC
R/W
R/W (see Note 1)
R/W
R/W
—
R/WC, RO, R/W
(see Note 1)
R/WC, RO, R/W
(see Note 1)
NOTES:
1.
These registers are WORD writable only. Byte writes to these registers have unpredictable
effects.
Intel ^® ICH7 Family Datasheet
479