307013-003 Datasheet, PDF (225/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.21.4 Interrupts / SMI#
The ICH7 SMBus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the
SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1).
Table 5-52 and Table 5-53 specify how the various enable bits in the SMBus function
control the generation of the interrupt, Host and Slave SMI, and Wake internal signals.
The rows in the tables are additive, which means that if more than one row is true for a
particular scenario then the Results for all of the activated rows will occur.
Table 5-51. Enable for SMBALERT#
Event
INTREN
(Host Control
I/O Register,
Offset 02h,
Bit 0)
SMBALERT#
X
asserted low
(always
reported in
X
Host Status
Register, Bit
5)
1
SMB_SMI_EN
(Host
Configuration
Register,
D31:F3:Offset
40h, Bit 1)
X
1
0
SMBALERT_DIS
(Slave Command
I/O Register,
Offset 11h, Bit 2)
Result
X
Wake generated
Slave SMI#
0
generated
(SMBUS_SMI_STS)
0
Interrupt
generated
Table 5-52. Enables for SMBus Slave Write and SMBus Host Events
Event
INTREN (Host
Control I/O
Register, Offset
02h, Bit 0)
SMB_SMI_EN (Host
Configuration
Register,
D31:F3:Offset 40h,
Bit1)
Event
Slave Write to
Wake/SMI#
X
Command
Slave Write to
SMLINK_SLAVE_S
X
MI Command
Any combination of
0
Host Status
Register [4:1]
1
asserted
1
Wake generated when
X
asleep.
Slave SMI# generated when
awake (SMBUS_SMI_STS).
Slave SMI# generated when
X
in the S0 state
(SMBUS_SMI_STS)
X
None
0
Interrupt generated
1
Host SMI# generated
Intel ^® ICH7 Family Datasheet
225