307013-003 Datasheet, PDF (804/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Electrical Characteristics
Table 23-11. IDE PIO Mode Timings
Sym
Parameter
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
(nS)
(nS)
(nS)
(nS)
(nS)
t60
t61
t62
t62i
t63
t64
t65
t66
t66z
t69
t60rd
t60a
t60b
t60c
Cycle Time (min)
Addr setup to DIOW#/
DIOR# (min)
DIRW#/DIOR# (min)
DIOW#/DIOR# recovery
time (min)
DIOW# data setup (min)
DIOW# data hold (min)
DIOR# data setup (min)
DIOR# data hold (min)
DIOR# data tristate (max)
DIOW#/DIOR# to address
valid hold (min)
Read data Valid to IORDY
active (min)
IORDY Setup
IORDY Pulse Width (max)
IORDY assertion to release
(max)
600
70
165
—
60
30
50
5
30
20
0
35
1250
5
383
50
125
—
45
20
35
5
30
15
0
35
1250
5
240
30
100
—
30
15
20
5
30
10
0
35
1250
5
180
30
80
70
30
10
20
5
30
10
0
35
1250
5
120
25
70
25
20
10
20
5
30
10
0
35
1250
5
Figure
23-7
23-7
23-7
23-7
23-7
23-7
23-7
23-7
23-7
23-7
23-7
23-7
23-7
23-7
Table 23-12. IDE Multiword DMA Timings
Sym
Parameter
t70
t70d
t70e
t70f
t70g
t70h
t70i
t70j
t70kr
t70kw
t70lr
t70lw
t70m
t70n
t70z
Cycle Time (min)
DIOR#/DIOW# (min)
DIOR# Data access (max)
DIOR# Data hold (min)
DIOR#/DIOW# Data setup (min)
DIOW# Data hold (min)
DDACK# to DIOR#/DIOW# setup (min)
DIOR#/DIOW# to DDACK# hold (min)
DIOR# negated pulse width (min)
DIOW# negated pulse width (min)
DIOR# to DDREQ delay (max)
DIOW# to DDREQ delay (max)
DCS1#/DCS3# valid to DIOR#/DIOW#
(min)
DCS1#/DCS3# hold (min)
DDACK# to tristate (max)
Mode 0
(nS)
480
215
150
5
100
20
0
20
50
215
120
40
50
15
20
Mode 1
(nS)
150
80
60
5
30
15
0
5
50
50
40
40
30
10
25
Mode 2
(nS)
120
70
50
5
20
10
0
5
25
25
35
35
25
10
25
Figure
23-8
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804
Intel ^® ICH7 Family Datasheet