307013-003 Datasheet, PDF (105/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
RCTL.PIE (D28:F0/F1/F2/F3/F4/F5:Offset 5Ch:bit 3), an interrupt will be generated.
This interrupt can be either a pin or a MSI if MSI is enabled via MC.MSIE (D28:F0/F1/
F2/F3/F4/F5:Offset 82h:bit 0). See Section 5.2.2.4 for SMI/SCI generation.
If this is a subsequent message received (RSTS.PS is already set), the root port will set
RSTS.PP (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit 17) and log the PME Requester ID
from the message in a hidden register. No other action will be taken.
When the first PME event is cleared by software clearing RSTS.PS, the root port will set
RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into
RSTS.RID.
If RCTL.PIE is set, generate an interrupt. If RCTL.PIE is not set, send over to the power
management controller so that a GPE can be set. If messages have been logged
(RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and interrupt must be
generated. This last condition handles the case where the message was received prior
to the operating system re-enabling interrupts after resuming from a low power state.
5.2.2.4
SMI/SCI Generation
Interrupts for power management events are not supported on legacy operating
systems. To support power management on non-PCI Express aware operating systems,
PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set.
When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/
F5:Offset DCh:bit 31) to be set.
Additionally, BIOS workarounds for power management can be supported by setting
MPC.PMME (D28:F0/F1/F2/F3/F4/F5:Offset D8h:bit 0). When this bit is set, power
management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 0),
and SMI # will be generated. This bit will be set regardless of whether interrupts or SCI
is enabled. The SMI# may occur concurrently with an interrupt or SCI.
5.2.3 SERR# Generation
SERR# may be generated via two paths – through PCI mechanisms involving bits in the
PCI header, or through PCI Express mechanisms involving bits in the PCI Express
capability structure.
Figure 5-1. Generation of SERR# to Platform
Secondary Parity Error
PCI
Primary Parity Error
Secondary SERR#
PCI Express
PCICMD.SEE
Correctable SERR#
Fatal SERR#
Non-Fatal SERR#
PSTS.SSE
SERR#
Intel ^® ICH7 Family Datasheet
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