307013-003 Datasheet, PDF (805/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Electrical Characteristics
Table 23-13. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 1 of 2)
Sym
1
Parameter
Mode 0
(ns)
Min Max
Mode 1
(ns)
Min Max
Mode 2
(ns)
Min Max
Measuring
Location
Figure
t80
Sustained Cycle Time
(T2cyctyp)
t81 Cycle Time (Tcyc)
t82 Two Cycle Time (T2cyc)
t83a Data Setup Time (Tds)
t83b
Recipient IC data setup time
(from data valid until STROBE
edge) (see Note ²) (Tdsic)
t84a Data Hold Time (Tdh)
t84b
Recipient IC data hold time
(from STROBE edge until data
may become invalid) (see
Note ²) (Tdhic)
t85a Data Valid Setup Time (Tdvs)
t85b
Sender IC data valid setup
time (from data valid until
STROBE edge) (see Note ²)
(Tdvsic)
t86a Data Valid Hold Time (Tdvh)
t86b
t87
t88
Sender IC data valid hold time
(from STROBE edge until data
may become invalid) (see
Note ²) (Tdvhic)
Limited Interlock Time (Tli)
Interlock Time w/ Minimum
(Tmli)
t89 Envelope Time (Tenv)
t90 Ready to Pause Time (Trp)
t91
DMACK setup/hold Time
(Tack)
t92a
CRC Word Setup Time at Host
(Tcvs)
240
112 —
230 —
15 —
14.
7
—
5—
4.8 —
70 —
72.
9
—
6.2 —
9—
0 150
20 —
20 70
160 —
20 —
70 —
160
73 —
153 —
10 —
9.7 —
5
—
4.8 —
48 —
50.
9
—
6.2 —
9
—
0 150
20 —
20 70
125 —
20 —
48 —
120
54 —
115 —
7—
6.8 —
Sender
Connector
End
Recipient
Connector
Sender
Connector
Recipient
Connector
Intel^® ICH7
ball
5
—
Recipient
Connector
4.8 — ICH7 ball
31
—
Sender
Connector
33.
9
—
ICH7 ball
6.2
—
Sender
Connector
9 — ICH7 ball
0 150 See Note 2
20
—
Host
Connector
20
70
Host
Connector
100 —
Recipient
Connector
20
—
Host
Connector
31
—
Host
Connector
23-10
23-10
23-10
23-10
23-10
23-10
23-12
23-12
23-9
23-11
23-9,
23-12
Intel ^® ICH7 Family Datasheet
805