307013-003 Datasheet, PDF (507/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.28 PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2)
Address Offset: 74h–75h
Default Value: 0000h
Attribute:
Size:
RO, R/W, R/WC
16 bits
Bits
Description
15
14:9
8
7:2
1:0
PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if
this bit and PMEE is set, a PME# will be generated from the SATA controller.
Reserved
PME Enable (PMEE) — R/W.
0 = Disable.
1 = Enable. SATA controller generates PME# form D3_HOT on a wake event.
Reserved
Power State (PS) — R/W. These bits are used both to determine the current power
state of the SATA controller and to set a new power state.
00 = D0 state
11 = D3_HOT state
When in the D3_HOT state, the controller’s configuration space is available, but the I/O
and memory spaces are not. Additionally, interrupts are blocked.
12.1.29 MSICI—Message Signaled Interrupt Capability
Identification (SATA–D31:F2)
Address Offset: 80h–81h
Default Value: 7005h
Attribute:
Size:
RO
16 bits
Bits
Description
15:8
7:0
Next Pointer (NEXT): Indicates the next item in the list is the PCI power management
pointer.
Capability ID (CID): Capabilities ID indicates MSI.
12.1.30 MSIMC—Message Signaled Interrupt Message Control
(SATA–D31:F2)
Address Offset: 82h–83h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bits
Description
15:8 Reserved
7 64 Bit Address Capable (C64): Capable of generating a 32-bit message only.
Intel ^® ICH7 Family Datasheet
507