307013-003 Datasheet, PDF (813/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Electrical Characteristics
Table 23-22. (Power Sequencing and Reset Signal Timings (Sheet 2 of 2)
Sym
Parameter
Min
Max Units Notes Fig
VccLAN supplies active to Vcc supplies
t212 active
(Mobile Only)
0
—
ms
5
23-19
VccSus supplies active to Vcc supplies
t213 ^active
(Desktop Only)
0
—
ms
3
23-18
23-18
Vcc supplies active to PWROK
23-19
23-20
t214 NOTE: PWROK assertion indicates that
PCICLK has been stable for at
least 1 ms.
99
—
ms
5, 7
23-21
23-23
23-24
23-25
23-26
V_CPU_IO active to STPCLK# and
t215 CPUSLP# inactive
(Desktop Only)
—
50
ns
23-20
23-23
23-24
t216
Vcc active to DPRSLPVR inactive and
STPCLK#, STP_CPU#, STP_PCI#,
DPSLP#, DPRSTP# inactive
(Mobile/Ultra Mobile Only)
—
50
ns
23-21
23-25
23-26
PWROK and VRMPWRGD active and
t217
SYS_RESET# inactive to SUS_STAT#
inactive and Processor I/F signals latched
32
to strap value
23-20
23-21
38
RTCCLK ^{8, 9}
23-23
23-24
23-25
23-26
t218 SUS_STAT# inactive to PLTRST# inactive
2
3
RTCCLK
9
23-20
23-21
23-23
23-24
23-25
23-26
t228 ACZ_RST# active low pulse width
1
—
us
t229
ACZ_RST# inactive to ACZ_BIT_CLK
startup delay
162.8
—
ns
NOTES:
1. 5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V.
2. The associated 3.3 V and 1.05 V supplies are assumed to power up or down ‘together’. If the integrated
VccSus1_05 voltage regulator is not used: a) VccSus3_3 must power up before VccSus1_05 or after
VccSus1_05 within 0.7 V, b) VccSus1_05 must power down before VccSus3_3 or after VccSus3_3 within 0.7 V.
3. The VccSus supplies must not be active while the VccRTC supply is inactive.
4. (Mobile Only) – a) VccLan3_3 must power up before VccLAN1_05 or after VccLAN1_05 within 0.7 V,
b) VccLAN1_05 must power down before VccLAN3_3 or after VccLAN3_3 within 0.7V.
5. (Mobile Only) - Vcc or VccLAN supplies must not be active while the VccSus supplies are inactive, and the Vcc
supplies must not be active while the VccLAN supplies are inactive.
6. Vcc1_5 must power up before V_CPU_IO or after V_CPU_IO within 0.7 V, b) V_CPU_IO must power down
before Vcc1_5 or after Vcc1_5 within 0.7 V.
7. Vcc supplies refer to all “core well” supplies: Vcc3_3, Vcc1_05, Vcc1_5, V5REF, VccUSBPLL, VccDMIPLL,
VccSATAPLL, V_CPU_IO and VccHDA (Mobile Only). It implies that all “suspend wells” and VccRTC are stable
too.
8. INIT# value determined by value of the CPU BIST Enable bit (Chipset Configuration Register Offset 3414h: bit
2).
9. These transitions are clocked off the internal RTC. 1 RTC clock is approximately from 28.992 µs to 32.044 µs.
Intel ^® ICH7 Family Datasheet
813