307013-003 Datasheet, PDF (171/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.14.10.1 Write Only Registers with Read Paths in ALT Access Mode
The registers described in Table 5-36 have read paths in ALT access mode. The access
number field in the table indicates which register will be returned per access to that
port.
Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)
Restore Data
Restore Data
I/O
Addr
# of
Rds
Access
Data
I/O
Addr
# of
Rds
Access
Data
00h
2
01h
2
02h
2
03h
2
04h
2
05h
2
06h
2
07h
2
1
DMA Chan 0 base address low
byte
2
DMA Chan 0 base address high
byte
1
DMA Chan 0 base count low
byte
2
DMA Chan 0 base count high
byte
40h
7
1
DMA Chan 1 base address low
byte
2
DMA Chan 1 base address high
byte
1
DMA Chan 1 base count low
byte
2
DMA Chan 1 base count high
byte
41h
1
1
DMA Chan 2 base address low
byte
42h
1
2
DMA Chan 2 base address high
byte
70h
1
1
DMA Chan 2 base count low
byte
C4h 2
2
DMA Chan 2 base count high
byte
1
DMA Chan 3 base address low
byte
C6h 2
2
DMA Chan 3 base address high
byte
1
DMA Chan 3 base count low
byte
C8h 2
2
DMA Chan 3 base count high
byte
1
Timer Counter 0 status, bits
[5:0]
2
Timer Counter 0 base count
low byte
3
Timer Counter 0 base count
high byte
4
Timer Counter 1 base count
low byte
5
Timer Counter 1 base count
high byte
6
Timer Counter 2 base count
low byte
7
Timer Counter 2 base count
high byte
Timer Counter 1 status, bits
[5:0]
Timer Counter 2 status, bits
[5:0]
Bit 7 = NMI Enable,
Bits [6:0] = RTC Address
1
DMA Chan 5 base address low
byte
2
DMA Chan 5 base address
high byte
1
DMA Chan 5 base count low
byte
2
DMA Chan 5 base count high
byte
1
DMA Chan 6 base address low
byte
2
DMA Chan 6 base address
high byte
Intel ^® ICH7 Family Datasheet
171