307013-003 Datasheet, PDF (74/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Signal Description
Table 2-21. General Purpose I/O Signals (Sheet 3 of 3)
Name^1,2
Type Tolerance
Power
Well
Default
Description
GPIO19
(Desktop and I/O
Mobile Only)
3.3 V
Core
GPI
Multiplexed with SATA1GP.
GPIO18
I/O
(Desktop Only)
3.3 V
Core
GPO
Mobile/Ultra Mobile Only: GPIO is
not implemented and is used
instead as STP_PCI#.
Desktop Only: Unmultiplexed.
GPIO17
I/O
3.3 V
Core
GPO
Multiplexed with GNT5#.
GPIO16
I/O
3.3 V
Core
Native
(Mobile/
Ultra
Mobile) /
GPO
(Desktop)
Mobile/Ultra Mobile Only:
Natively used as DPRSLPVR.
Desktop Only: Unmultiplexed.
GPIO[15:12]
I/O
3.3 V
Resume
GPI
Unmultiplexed.
GPIO11
I/O
3.3 V
Resume
Native Multiplexed with SMBALERT#
GPIO[10:8]
I/O
3.3 V
Resume
GPI
Unmultiplexed.
GPIO[7:6]
I/O
3.3 V
Core
GPI
Unmultiplexed.
GPIO[5:2]
I/OD
5V
Core
GPI
Multiplexed with PIRQ[H:E]#.
GPIO1
I/O
5V
Core
GPI
Multiplexed with REQ5#.
GPIO0
I/O
(Desktop Only)
3.3 V
Core
Mobile/Ultra Mobile Only:
GPI
Multiplexed with BM_BUSY#.
Desktop Only: Unmultiplexed
NOTES:
1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI,
but not both.
2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not driven
high into powered-down planes. Some ICH7 GPIOs may be connected to pins on devices that exist in the core
well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button
Override event will result in the Intel ICH7 driving a pin to a logic 1 to another device that is powered down.
2.23 Power and Ground
Table 2-22. Power and Ground Signals (Sheet 1 of 3)
Name
Description
Vcc3_3
Vcc1_05
Vcc1_5_A
Vcc1_5_B
V5REF
(Desktop and
Mobile Only)
These pins provide the 3.3 V supply for core well I/O buffers (22pins). This
power may be shut off in S3, S4, S5 or G3 states.
These pins provide the 1.05 V supply for core well logic (20 pins). This power
may be shut off in S3, S4, S5 or G3 states.
These pins provide the 1.5 V supply for Logic and I/O (30 pins). This power may
be shut off in S3, S4, S5 or G3 states.
These pins provide the 1.5 V supply for Logic and I/O (53 pins). This power may
be shut off in S3, S4, S5 or G3 states.
These pins provide the reference for 5 V tolerance on core well inputs (2 pins).
This power may be shut off in S3, S4, S5 or G3 states.
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Intel ^® ICH7 Family Datasheet