307013-003 Datasheet, PDF (537/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Bit
Description
FIS Receive Enable (FRE) — R/W. When set, the ICH7 may post received FISes into
the FIS receive area pointed to by PxFB (ABAR+108h/188h/208h/288h) and PxFBU
(ABAR+10Ch/18Ch/20Ch/28Ch). When cleared, received FISes are not accepted by the
ICH7, except for the first D2H (device-to-host) register FIS after the initialization
4 ^sequence.
System software must not set this bit until PxFB (PxFBU) have been programmed with a
valid pointer to the FIS receive area, and if software wishes to move the base, this bit
must first be cleared, and software must wait for the FR bit (bit 14) in this register to be
cleared.
Command List Override (CLO) — R/W. Setting this bit to '1' causes PxTFD.STS.BSY and
PxTFD.STS.DRQ to be cleared to '0'. This allows a software reset to be transmitted to
the device regardless of whether the BSY and DRQ bits are still set in the PxTFD.STS
register. The HBA sets this bit to '0' when PxTFD.STS.BSY and PxTFD.STS.DRQ have
3 _{been cleared to '0'. A write to this register with a value of '0' shall have no effect.}
This bit shall only be set to '1' immediately prior to setting the PxCMD.ST bit to '1' from
a previous value of '0'. Setting this bit to '1' at any other time is not supported and will
result in indeterminate behavior
2 Power On Device (POD) — RO. Cold presence detect not supported. Defaults to 1.
Spin-Up Device (SUD) — R/W / RO. This bit is R/W and defaults to 0 for systems that
support staggered spin-up (R/W when CAP.SSS (ABAR+00h:bit 27) is 1). Bit is RO 1 for
systems that do not support staggered spin-up (when CAP.SSS is 0).
1
0 = No action.
1 = On an edge detect from 0 to 1, the ICH7 starts a COMRESET initialization sequence
to the device.
Start (ST) — R/W. When set, the ICH7 may process the command list. When cleared,
the ICH7 may not process the command list. Whenever this bit is changed from a 0 to a
1, the ICH7 starts processing the command list at entry 0. Whenever this bit is changed
0 ^{from a 1 to a 0, the PxCI register is cleared by the ICH7 upon the ICH7 putting the}
controller into an idle state.
Refer to section 10.3.1 of the Serial ATA AHCI Specification for important restrictions on
when ST can be set to 1.
Intel ^® ICH7 Family Datasheet
537