307013-003 Datasheet, PDF (450/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
Bit
Description
INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of
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the SMI status bits in the Intel-Specific USB2 SMI Status Register ANDed with the
corresponding enable bits. This bit will not be active if the enable bits are not set.
Writes to this bit will have no effect.
LEGACY_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each
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of the SMI status bits in the USB2 Legacy Support Register ANDed with the
corresponding enable bits. This bit will not be active if the enable bits are not set.
Writes to this bit will have no effect.
SMBus SMI Status (SMBUS_SMI_STS) — R/WC. Software clears this bit by
writing a 1 to it.
0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software
must wait at least 15.63 us after the initial assertion of this bit before clearing
it.
1 = Indicates that the SMI# was caused by:
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1. The SMBus Slave receiving a message that an SMI# should be caused, or
2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
SMBALERT_DIS bit is cleared, or
3. The SMBus Slave receiving a Host Notify message and the
HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or
4. The ICH7 detecting the SMLINK_SLAVE_SMI command while in the S0
state.
SERIRQ_SMI_STS — RO.
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0 = SMI# was not caused by the SERIRQ decoder.
1 = Indicates that the SMI# was caused by the SERIRQ decoder.
NOTE: This is not a sticky bit
PERIODIC_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = Software clears this bit by writing a 1 to it.
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1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the
PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the Intel^® ICH7
generates an SMI#.
TCO_STS — R/WC. Software clears this bit by writing a 1 to it.
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0 = SMI# not caused by TCO logic.
1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake
event.
Device Monitor Status (DEVMON_STS) — RO.
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0 = SMI# not caused by Device Monitor.
1 = Set if bit 0 of the DEVACT_STS register (PMBASE + 44h) is set. The bit is not
sticky, so writes to this bit will have no effect.
Microcontroller SMI# Status (MCSMI_STS) — R/WC. Software clears this bit
by writing a 1 to it.
0 = Indicates that there has been no access to the power management
microcontroller range (62h or 66h).
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1 = Set if there has been an access to the power management microcontroller
range (62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC
Bridge I/O Enables configuration register is 1 (D31:F0:Offset 82h:bit 11).
Note that this implementation assumes that the Microcontroller is on LPC. If
this bit is set, and the MCSMI_EN bit is also set, the ICH7 will generate an
SMI#.
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Intel ^® ICH7 Family Datasheet