307013-003 Datasheet, PDF (423/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
Bit
Description
RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RTCRST# indicates
2 a weak or missing battery. The bit is not cleared by any type of reset. The bit will
remain set until the software clears it by writing a 0 back to this bit position.
Power Failure (PWR_FLR) — R/WC. This bit is in the RTC well, and is not cleared by
any type of reset except RTCRST#.
0 = Indicates that the trickle current has not failed since the last time the bit was
cleared. Software clears this bit by writing a 1 to it.
1
1 = Indicates that the trickle current (from the main battery or trickle supply) was
removed or failed.
NOTE: Clearing CMOS in an ICH-based platform can be done by using a jumper on
RTCRST# or GPI, or using SAFEMODE strap. Implementations should not
attempt to clear CMOS by using a jumper to pull VccRTC low.
AFTERG3_EN — R/W. This bit determines what state to go to when power is re-applied
after a power failure (G3 state). This bit is in the RTC well and is not cleared by any
type of reset except writes to CF9h or RTCRST#.
0 = System will return to S0 state (boot) after power is re-applied.
0 1 = System will return to the S5 state (except if it was in S4, in which case it will return
to S4). In the S5 state, the only enabled wake event is the Power Button or any
enabled wake event that was preserved through the power failure.
NOTE: Bit will be set when THRMTRIP#-based shutdown occurs.
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC
clock period may not be detected by the ICH7.
Intel ^® ICH7 Family Datasheet
423