307013-003 Datasheet, PDF (478/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

UHCI Controllers Registers
11.1.18 USB_RES—USB Resume Enable Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
C4h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:2 Reserved
PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events.
1 ^{0 = The USB controller will not look at this port for a wakeup event.}
1 = The USB controller will monitor this port for remote wakeup and connect/
disconnect events.
PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events.
0 ^{0 = The USB controller will not look at this port for a wakeup event.}
1 = The USB controller will monitor this port for remote wakeup and connect/
disconnect events.
11.1.19 CWP—Core Well Policy Register
(USB—D29:F0/F1/F2/F3)
Address Offset: C8h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:1 Reserved
Static Bus Master Status Policy Enable (SBMSPE) — R/W.
0 = The UHCI host controller dynamically sets the Bus Master status bit (Power
Management 1 Status Register,[PMBASE+00h], bit 4) based on the memory
accesses that are scheduled. For mobile/Ultra Mobile only, the default setting
provides a more accurate indication of snoopable memory accesses in order to help
with software-invoked entry to C3 and C4 power states.
0 _{1 = The UHCI host controller statically forces the Bus Master Status bit in power}
management space to 1 whenever the HCHalted bit (USB Status Register,
Base+02h, bit 5) is cleared.
NOTE: The PCI Power Management registers are enabled in the PCI Device 31:
Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte
aligned).
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Intel ^® ICH7 Family Datasheet