307013-003 Datasheet, PDF (561/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

EHCI Controller Registers (D29:F7)
13.2 Memory-Mapped I/O Registers
Note:
Note:
The EHCI memory-mapped I/O space is composed of two sets of registers: Capability
Registers and Operational Registers.
The ICH7 EHCI controller will not accept memory transactions (neither reads nor
writes) as a target that are locked transactions. The locked transactions should not be
forwarded to PCI as the address space is known to be allocated to USB.
When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory
range are ignored and result a master abort. Similarly, if the Memory Space Enable
(MSE) bit (D29:F7:04h, bit 1) is not set in the Command register in configuration
space, the memory range will not be decoded by the ICH7 enhanced host controller
(EHC). If the MSE bit is not set, then the ICH7 must default to allowing any memory
accesses for the range specified in the BAR to go to PCI. This is because the range may
not be valid and, therefore, the cycle must be made available to any other targets that
may be currently using that range.
13.2.1 Host Controller Capability Registers
These registers specify the limits, restrictions and capabilities of the host controller
implementation. Within the host controller capability registers, only the structural
parameters register is writable. These registers are implemented in the suspend well
and is only reset by the standard suspend-well hardware reset, not by HCRESET or the
D3-to-D0 reset.
Table 13-2. Enhanced Host Controller Capability Registers
MEM_BAS
E + Offset
Mnemonic
Register
00h
02h–03h
CAPLENGTH Capabilities Registers Length
HCIVERSION
Host Controller Interface Version
Number
Default
20h
0100h
04h–07h HCSPARAMS Host Controller Structural Parameters 00104208h
08h–0Bh HCCPARAMS Host Controller Capability Parameters 00006871h
Type
RO
RO
R/W
(special),
RO
RO
NOTE: “Read/Write Special” means that the register is normally read-only, but may be written
when the WRT_RDONLY bit is set. Because these registers are expected to be programmed
by BIOS during initialization, their contents must not get modified by HCRESET or D3-to-
D0 internal reset.
13.2.1.1
CAPLENGTH—Capability Registers Length Register
Offset:
MEM_BASE + 00h
Default Value: 20h
Attribute:
Size:
RO
8 bits
Bit
Description
Capability Register Length Value — RO. This register is used as an offset to add to the
7:0
Memory Base Register (D29:F7:10h) to find the beginning of the Operational Register
Space. This field is hardwired to 20h indicating that the Operation Registers begin at
offset 20h.
Intel ^® ICH7 Family Datasheet
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