307013-003 Datasheet, PDF (366/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.1.5
Bit
11
10:9
8
7
6
5
4
3
2:0
Description
Signaled Target Abort (STA) — R/WC.
0 = Target abort Not generated on the backbone.
1 = LPC bridge generated a completion packet with target abort status on the
backbone.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Medium Timing.
Data Parity Error Detected (DPED) — R/WC.
0 = All conditions listed below Not met.
1 = Set when all three of the following conditions are met:
• LPC bridge receives a completion packet from the backbone from a previous request,
• Parity error has been detected (D31:F0:06, bit 15)
• PCICMD.PERE bit (D31:F0:04, bit 6) is set.
Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal
backbone.
Reserved.
66 MHz Capable (66MHZ_CAP) — Reserved – bit has no meaning on internal
backbone.
Capabilities List (CLIST) — RO. Capability list exists on the LPC bridge.
Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts.
Reserved.
RID—Revision Identification Register (LPC I/F—D31:F0)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
10.1.6
Bit
Description
7:0
Revision ID (RID) — RO. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family
Specification Update for the value of the Revision ID Register.
PI—Programming Interface Register (LPC I/F—D31:F0)
Offset Address: 09h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Programming Interface — RO.
366
Intel ^® ICH7 Family Datasheet