307013-003 Datasheet, PDF (533/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.3.2.6
Bit
Description
21:8
7
6
5
4
3
2
1
0
Reserved
Device Interlock Status (DIS) — R/WC. When set, indicates that a platform interlock
switch has been opened or closed, which may lead to a change in the connection state
of the device.This bit is only valid in systems that support an interlock switch (CAP.SIS
[ABAR+00:bit 28] set).
For systems that do not support an interlock switch, this bit will always be 0.
Port Connect Change Status (PCS) — RO. This bit reflects the state of
PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this
register, this bit is only cleared when PxSERR.DIAG.X is cleared.
0 = No change in Current Connect Status.
1 = Change in Current Connect Status.
Descriptor Processed (DPS) — R/WC. A PRD with the I bit set has transferred all its
data.
Unknown FIS Interrupt (UFS) — RO. When set to ‘1’ indicates that an unknown FIS
was received and has been copied into system memory. This bit is cleared to ‘0’ by
software clearing the PxSERR.DIAG.F bit to ‘0’. Note that this bit does not directly
reflect the PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an unknown
FIS is detected, whereas this bit is set when the FIS is posted to memory. Software
should wait to act on an unknown FIS until this bit is set to ‘1’ or the two bits may
become out of sync.
Set Device Bits Interrupt (SDBS) — R/WC. A Set Device Bits FIS has been received
with the I bit set and has been copied into system memory.
DMA Setup FIS Interrupt (DSS) — R/WC. A DMA Setup FIS has been received with
the I bit set and has been copied into system memory.
PIO Setup FIS Interrupt (PSS) — R/WC. A PIO Setup FIS has been received with the
I bit set, it has been copied into system memory, and the data related to that FIS has
been transferred.
Device to Host Register FIS Interrupt (DHRS) — R/WC. A D2H Register FIS has
been received with the I bit set, and has been copied into system memory.
PxIE—Port [3:0] Interrupt Enable Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 114h
Attribute:
R/W, RO
Port 1: ABAR + 194h (ICH7R and ICH7DH Only)
Port 2: ABAR + 214h
Port 3: ABAR + 294h (ICH7R and ICH7DH Only)
00000000h
Size:
32 bits
This register enables and disables the reporting of the corresponding interrupt to
system software. When a bit is set (‘1’) and the corresponding interrupt condition is
active, then an interrupt is generated. Interrupt sources that are disabled (‘0’) are still
reflected in the status registers.
Bit
Description
31 Cold Presence Detect Enable (CPDE) — RO. Cold Presence Detect not supported.
Task File Error Enable (TFEE) — R/W. When set, and GHC.IE and PxTFD.STS.ERR
30 (due to a reception of the error register from a received FIS) are set, the Intel^® ICH7
will generate an interrupt.
29
Host Bus Fatal Error Enable (HBFE) — R/W. When set, and GHC.IE and PxS.HBFS
are set, the ICH7 will generate an interrupt.
Intel ^® ICH7 Family Datasheet
533