307013-003 Datasheet, PDF (420/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.1.2
Bit
Description
3
(Mobile/
Ultra
Mobile
Only)
2
(Mobile/
Ultra
Mobile
Only)
1:0
Intel SpeedStep Enable (SS_EN) — R/W.
0 = Intel SpeedStep technology logic is disabled and the SS_CNT register will not be
visible (reads to SS_CNT will return 00h and writes will have no effect).
1 = Intel SpeedStep technology logic is enabled.
PCI CLKRUN# Enable (CLKRUN_EN) — R/W.
0 = Disable. Intel^® ICH7-M/ICH7-U drives the CLKRUN# signal low.
1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and
STP_PCI# signals.
NOTE: when the SLP_EN# bit is set, the ICH7 drives the CLKRUN# signal low
regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and
LPC clocks continue running during a transition to a sleep state.
Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control
the rate at which periodic SMI# is generated.
00 = 1 minute
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)
Offset Address: A2h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, R/WC
8-bit
ACPI, Legacy
Resume
Bit
Description
DRAM Initialization Bit — R/W. This bit does not effect hardware functionality in any
way. BIOS is expected to set this bit prior to starting the DRAM initialization sequence
and to clear this bit after completing the DRAM initialization sequence. BIOS can detect
7 that a DRAM initialization sequence was interrupted by a reset by reading this bit during
the boot sequence.
• If the bit is 1, then the DRAM initialization was interrupted.
• This bit is reset by the assertion of the RSMRST# pin.
CPU PLL Lock Time (CPLT) — R/W. This field indicates the amount of time that the
processor needs to lock its PLLs. This is used wherever timing t270 (Chapter 23)
applies.
00 = min 30.7 µs (Default)
01 = min 61.4 µs
10 = min 122.8 µs
6:5 ^{11 = min 245.6 µs}
It is the responsibility of the BIOS to program the correct value in this field prior to the
first transition to C3 or C4 states (or performing Intel SpeedStep^® technology
transitions).
NOTE: The new DPSLP-TO-SLP bits (D31:FO:AAh, bits 1:0) act as an override to these
bits.
NOTE: These bits are not cleared by any type of reset except RSMRST# or a CF9 write
420
Intel ^® ICH7 Family Datasheet