307013-003 Datasheet, PDF (567/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

EHCI Controller Registers (D29:F7)
Bit
Description
Run/Stop (RS) — R/W.
0 = Stop (default)
1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule.
The Host controller continues execution as long as this bit is set. When this bit is
set to 0, the Host controller completes the current transaction on the USB and then
halts. The HCHalted bit in the USB2.0_STS register indicates when the Host
controller has finished the transaction and has entered the stopped state.
Software should not write a 1 to this field unless the host controller is in the Halted
state
(i.e., HCHalted in the USBSTS register is a 1). The Halted bit is cleared immediately
when the Run bit is set.
0 ^{The following table explains how the different combinations of Run and Halted should}
be interpreted:
Run/Stop
0b
0b
1b
1b
Halted
0b
1b
0b
1b
Interpretation
In the process of halting
Halted
Running
Invalid - the HCHalted bit clears
immediately
Memory read cycles initiated by the EHC that receive any status other than Successful
will result in this bit being cleared.
NOTE: The Command Register indicates the command to be executed by the serial bus host
controller. Writing to the register causes a command to be executed.
Intel ^® ICH7 Family Datasheet
567