307013-003 Datasheet, PDF (499/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.18 CAP—Capabilities Pointer Register (SATA–D31:F2)
Address Offset: 34h
Default Value: 80h
Attribute:
Size:
RO
8 bits
Bit
Description
Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer offset is
80h. This value changes to 70h if the MAP.MV register (Dev 31:F2:90h, bits 1:0) in
7:0 configuration space indicates that the SATA function and PATA functions are combined
(values of 10b or 10b) or Sub Class Code (CC.SCC) (Dev 31:F2:0Ah) is configure as IDE
mode (value of 01).
12.1.19 INT_LN—Interrupt Line Register (SATA–D31:F2)
Address Offset: 3Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
Interrupt Line — R/W. This field is used to communicate to software the interrupt line
that the interrupt pin is connected to.
12.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F2)
Address Offset: 3Dh
Attribute:
Default Value: See Register Description Size:
RO
8 bits
Bit
Description
Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Config
7:0 Registers:Offset 3100h:
bits 11:8).
12.1.21 IDE_TIMP — Primary IDE Timing Register (SATA–D31:F2)
Address Offset: Primary: 40h–41h
Secondary: 42h–43h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
transfers. It also controls operation of the buffer for PIO transfers.
Note:
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation unless otherwise noted.
Intel ^® ICH7 Family Datasheet
499