307013-003 Datasheet, PDF (302/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
Bit
Description
AC ‘97 Static Clock Gate Enable — R/W.
0 = AC ‘97 Static Clock Gating is Disabled
23
1 = AC ‘97 Static Clock Gating is Enabled
27:23
22
21
20
19
18:17
16
15:4
3
2
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
Reserved
High Definition Audio Dynamic Clock Gate Enable — R/W.
0 = HIgh Definition Audio Dynamic Clock Gating is Disabled
1 = HIgh Definition Audio Dynamic Clock Gating is Enabled
High Definition Audio Static Clock Gate Enable — R/W.
0 = HIgh Definition Audio Static Clock Gating is Disabled
1 = HIgh Definition Audio Static Clock Gating is Enabled
USB EHCI Static Clock Gate Enable — R/W.
0 = USB EHCI Static Clock Gating is Disabled
1 = USB EHCI Static Clock Gating is Enabled
USB EHCI Dynamic Clock Gate Enable — R/W.
0 = USB EHCI Dynamic Clock Gating is Disabled
1 = USB EHCI Dynamic Clock Gating is Enabled
Reserved
PCI Dynamic Gate Enable — R/W. Funcitonality reserved. BIOS must ensure bit is
0.
Reserved
DMI and PCI Express* RX Dynamic Clock Gate Enable — R/W.
0 = DMI and PCI Express root port RX Dynamic Clock Gating is Disabled
1 = DMI and PCI Express root port RX Dynamic Clock Gating is Enabled
PCI Express TX Dynamic Clock Gate Enable — R/W.
0 = PCI Express root port TX Dynamic Clock Gating is Disabled
1 = PCI Express root port TX Dynamic Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
DMI TX Dynamic Clock Gate Enable — R/W.
1
0 = DMI TX Dynamic Clock Gating is Disabled
1 = DMI TX Dynamic Clock Gating is Enabled
PCI Express Root Port Static Clock Gate Enable — R/W.
0 = PCI Express root port Static Clock Gating is Disabled
0
1 = PCI Express root port Static Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
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Intel ^® ICH7 Family Datasheet